A memory device, such as a dynamic random access memory (DRAM) device, can include memory cells each configured to store a binary data bit (1 or 0) and produce a signal on a bit line that represents the data bit. To read the data bit from a memory cell, a sense amplifier can be used to amplify the signal on the bit line to a level allowing for reliable detection of the data bit as “1” (logic high) or “0” (logic low). Some memory devices can store data bits having more than two logic levels. For example, a 3-level DRAM may store data bits having logic levels corresponding to Vcc (DRAM supply voltage), Vcc/2, and 0. This allows each data bit to have a third state in addition to the logic high and low states.